Exemplary embodiments of the present invention relate to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device with buried bit lines and a method for fabricating the same.
In order to decrease the size of a memory device, three-dimensional (3D) cells of 4F2 (where F denotes a minimum feature size) are under development. Examples of the 3D cells include vertical cells.
A vertical cell includes a pillar-type active region, a buried bit line filling a portion of a trench that isolates the active region, and a vertical gate formed on a sidewall of the active region.
FIG. 1 is a cross-sectional view illustrating vertical cells of a known semiconductor device.
Referring to FIG. 1, a plurality of active regions 12 are formed over a substrate 11. Each active region 12 has a plurality of sidewalls, and each sidewall has a vertical profile. The inside of a trench 13, which isolates neighboring active regions 12, is partially flied with a buried bit line 14. Also, a junction 15 is formed on each active region 12. The junction 15 contacts the buried bit line 14. An insulation layer 16 provides a contact portion between the junction 15 and the buried bit line 14, and the insulation layer 16 covers the surface of each active region 12 and each hard mask layer 17.
The junction 15 is formed at a portion of any one sidewall of the active region 12 in order to form the metallic buried bit line 14 that stably contacts the junction 15. Also, since the buried bit line 14 has a shape filling the lower portion of the trench 13, the height of the junction 15 should be positioned in the lower portion of the sidewall of the active region 12.
However, it is difficult to consistently create a junction 15 at a certain height along any one sidewall of each of the active regions 12. In order to do so, a great number of mask processes and other fabrication processes may be required. In particular, as the size of semiconductor devices decreases, misalignment of the junctions 15 in each of the active regions 12 may occur more often. Also, attempting to align the junctions 15 in each of the active regions 12 may be disadvantageous in terms of throughput because difficult processes, such as stripping, deposition, and etching, are repeatedly performed.
Moreover, since the active regions 12 are formed to have a predetermined height with a narrow space between them, it is even more difficult to form the junction 15 on a portion of one sidewall of the active regions 12. Forming the junction 15 may require a tilt ion implantation process. To perform the tilt ion implantation process, the substrate 11, having the active regions 12 and trenches 13 is placed at an angle with respect to the ion implantation process. Because the space between the active regions 12 is narrow, a shadow effect may occur during the tilt ion implantation process. Due to the shadow effect, ions may not be implanted into a target position and the depth of the junction 15 may not be uniform.